Clock extracting circuit

クロック抽出回路

Abstract

【課題】外部より受信した符号化信号からクロック信号を適切に抽出する。 【解決手段】伝送対象のデジタル信号をクロック信号に基づいて符号化した符号化信号を受信して当該符号化信号から前記クロック信号を抽出するクロック抽出回路において、受信した前記符号化信号の立ち上がりエッジ及び立ち下がりエッジを検出して当該検出した旨を示すエッジ検出パルスを生成するエッジ検出部と、前記受信した符号化信号の一周期毎に生成される前記エッジ検出パルスに基づいて、前記一周期毎の前記エッジ検出パルスの生成を契機として位相反転されるマスク信号を生成するマスク信号生成部と、制御可能な遅延時間分、前記マスク信号を遅延させたマスク遅延信号を生成するマスク信号遅延部と、前記マスク遅延信号のエッジに基づいて前記クロック信号を生成するクロック生成部と、前記生成されたクロック信号のデューティ比を所定値に設定すべく、前記マスク信号遅延部の遅延時間を制御する遅延制御部と、を有する。 【選択図】 図1
<P>PROBLEM TO BE SOLVED: To properly extract a clock signal from an encoded signal which is received from the outside. <P>SOLUTION: A clock extracting circuit which receives the encoded signal generated by encoding a digital signal to be transmitted, based upon the clock signal and extracts the clock signal from the encoded signal, has an edge detection section which detects a leading edge and a trailing edge of the received encoded signal and generates an edge detection pulse indicating the detection, a mask signal generation section which generates a mask signal inverted in phase in response to the generation of the edge detection pulse in every cycle, based upon the edge detection pulse generated in every cycle of the received encoded signal, a mask signal delay section which generates a mask delay signal by delaying the mask signal by a controllable delay time, a clock generation section which generates the clock signal based upon edges of the mask delay signal, and a delay control section which controls the delay time of the mask signal delay section to set the duty ratio of the generated clock signal to a designated value. <P>COPYRIGHT: (C)2006,JPO&NCIPI

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