clock (Total 56186 Patents Found)

Clock (56186 Patents Found)
A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is ...
A radio (100) having an integrated transceiver circuit (102) avoids circuit crosstalk through the use of a clock shifter circuit (120). The radio includes a microcontroller unit (MCU) (104) controlled by a MCU clock. A channel selector (116) coupled to the MCU (104) provides a selected frequency channel while memory (1...
Methods and apparatus for rapidly and automatically syntonizing the frequency of a passive atomic resonator of an atomic clock with a reference frequency which corresponds to the frequency of an external reference signal. Any difference between the hyperfine transition frequency of the resonator and the reference frequ...
A methodology is implemented for accurately and precisely computing the output signal times for clock circuit in a data processing system ( 600 ) using transistor-level static timing analysis tools which compute delays of blocks or subcircuits that correspond to channel-connected components of transistors. During execu...
A multi-clock matched filter for receiving signals with multipath. The signals may be modulated with a spread-spectrum spreading sequence, or other analog or digital signal. A number of signal registers store digital samples of the received signal. The gating of digital samples into each of the signal registers is cont...
A stepping motor driving apparatus of an analog electronic clock, in which, when the rotation of a rotor is not detected after a pulse is supplied to a coil of a stepping motor, a first switching control section switches the pulse supplied to the coil to a pulse having a larger effective value, and when the rotation of...
Methods and systems for resolving clock management issues in emulation of a target system on a host system are disclosed. A first set of code instructions of a target program is interpreted to generate interpreted code instructions that emulate a first component on the host system. A second set of code instructions is ...
An automatic test system configured for generating a periodic signal of a programmable frequency. The automatic test system may comprise a clock, an edge generator coupled to the clock, a phase locked loop, and a delay adjustment circuit. The edge generator may comprise an edge generator output, an enable input and a d...
A clock generation device measures a frequency ratio between a clock signal CK 1 (32.768 kHz+α) and a reference frequency value based on a clock signal CK 3 (25 MHz), generates a clock signal CK 2 obtained by masking at least one clock pulse of the clock signal CK 1 based on the measurement result of the frequency...
Systems and methods for a wafer scale atomic clock are provided. In at least one embodiment, a wafer scale device comprises a first substrate; a cell layer joined to the first substrate, the cell layer comprising a plurality of hermetically isolated cells, wherein separate measurements are produced for each cell in the...
A synchronized clock system, for use with an electronic system having several system nodes requiring a synchronized clock signal. The clock system may be formed in either discrete form or in integrated form, or in any combination, and includes a first synch bus and a second synch bus, isolated from the first synch bus,...
A peak phase error circuit including phase difference logic and delay and register logic. The phase difference logic provides a pulse difference signal including at least one difference pulse indicative of a timing difference between selected edges of a pair of clock signals. The delay and register logic receives the p...
A charge pump is connected to receive a supply voltage and a clock signal and generate an output voltage. The charge pump is connected to the supply voltage through a transistor whose gate voltage is set by a regulation voltage determined by feedback from the output voltage. The current supplied to the charge pump thro...
A circuit for performing clock recovery according to a received digital signal 30. The circuit includes at least an edge sampler 105 and a data sampler 145 for sampling the digital signal, and a clock signal supply circuit. The clock signal supply circuit provides edge clock 25 and data clock 20 signals offse...
A data driver including a receiver, a skew adjusting circuit and a processing device is provided. The receiver samples image data on a data bus according to a processed pixel clock signal. The image data includes pixel data during active periods and a test pattern repeatedly inserted in the image data during blanking p...
Circuit for detecting malfunction of a primary clock in SoCs comprises a primary clock circuit having a GRAY code counter for generating a GRAY code sequence based on a number of clock pulses generated Primary clock. A secondary clock circuit is configured to output a secondary clock pulse on each saturation of a secon...
The present invention introduces methods, systems, and architectures for routing clock signals in an integrated circuit layout. The introduced clock signal clock signal structures are rendered with non Manhattan routing. In a first embodiment, the traditional recursive H clock signal structure is rendered after transfo...
A variable frequency clock generator provides complementary phase clock signals for a microprocessor (10) at a selectable one of a plurality of frequencies. The outputs (PH10, PH20) may be dynamically switched between any of the frequencies so that every cycle of the phase clock signals has a duration at least as great...